signal vs. variable
(1) Physical meaning
Signals represent physical interconnect (wire) that communicate between processes (functions).
Variable do not has physical meanings, not exist in real circuits, mainly used for simulation, represent local storage. Like a variable in C or Pascal, a variable in VHDL carries with it only one piece of information: its current value.
(2) Delay
Signals assignment can have delays, update at the end of the process.It is important to realize that even without an after clause, all signal assignments occur with some infinitesimal delay, known as delta delay. Technically, delta delay is of no measurable unit, but from a hardware design perspective you should think of delta delay as being the smallest time unit you could measure, such as a femtosecond.
Variable assignments are updated immediately
(3) Defination
Signal can not be defined in process and subprogram(including fuction and procedure), must be defined outside them
Variable can only be difined in process and subprogram(including fuction and procedure),should not be defined outside.
The following is two classic examples to explain to differents between signal and variable
----------For signals-----------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY C1 is
PORT( IP: in std_logic;
CP: in std_logic;
OP: out std_logic
);
END C1;
ARCHITECTURE a OF C1 IS
signal d : std_logic;
BEGIN
process(CP,IP)
begin
if CP'event and CP='1' then
D<=IP;
OP<=D;
end if;
end process;
END a;
_________For variable_________________________
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY C2 is
PORT( IP: in std_logic;
CP: in std_logic;
OP: out std_logic
);
END C2;
ARCHITECTURE a OF C2 IS
BEGIN
process(CP,IP)
variable D: std_logic;
begin
if CP'event and CP='1' then
D:=IP;
OP<=D;
end if;
end process;
END a;