how to use pmos as capacitor

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gate is a terminal (usually plus) and source+bulk+drain is the other terminal (usually minus)
 
Are you creating layout or are you using an IC?
If you are using an IC like the CD4007 you need to remember to connect the VDD terminal as part of your circuit otherwise it will not work. If you are creating layout, you should do what the user above said.
 
In addition,you should be aware that the effective capacitor value of such configuration is vlotage depended.
 
safwatonline said:
gate is a terminal (usually plus) and source+bulk+drain is the other terminal (usually minus)
Click to expand...

this one convinces and i already know that. i'm just curious if there are any other solutions without using ICs. i'm referring to a schematic for IC layout.
 

gate in the lowest voltage
other end in the higher voltage
 

but u have to bias in a proper range , depending upon the signal magnitude .
 

safwatonline said:
gate is a terminal (usually plus) and source+bulk+drain is the other terminal (usually minus)
Click to expand...

good
 

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