I am a newbie,I don't know afer layout what file foundry will give to me,and how to use it in ncsim and ambit and the file have what data. or JUST SDF file?
You need the Design Kit(std cell lib) provided from foundry at least.
There are 2 ways to tapeout:
1. ASIC design-in, you release the synthesized netlist to foundry, they do the P&R / Clocktree Insertion / Extraction / Fix / Check jobs and return the sdf and new netlist file to you for timing and func check.
2. GDS tapeout, you do all the backend jobs and release GDSII file to the foundry, no return from foundry except wafers.
Hi, xworld2008
you can change your synthesis environment or your synthesis constraints so that more efficiently conform to the real world . Or change your design code or your design architecture. nothing else.