How to use nmosdnw transistor in layout

[mahdiiust]

Hi
I must connect source and body terminals of all transistor to each other to obtain proper result in hspice.
but when i draw the layout i encountered a problem.
for pmos transistor it's ok because pmos transistors are in seperate wells and i can connect source and body to each other.
but for nmos transistor it's not! :-?
for those nmos transistors which their sources are not connected to Vss, the body is connected to Vss becuase all nmos transistors are in psub.
to solve this problem I try to isolate nmos from psub using nmosdnw transistors. but unfortunately the LVS isn't pass.
is there any important notice in using nmosdnw?I use TSMC0.18rf technology. can somebody help me?
thanks

 

[Dominik Przyborowski]

You have to add at the schematic a proper diodes (probably DP and DN) between substrate and bulk of dnwnfet and betweent bulk and vdd.

 

[mahdiiust]

You have to add at the schematic a proper diodes (probably DP and DN) between substrate and bulk of dnwnfet and betweent bulk and vdd.

thank you for your answer!
but I can't realize what you mean.
for example I change my schematic and layout as figures below.
but it's LVS failed!

 

[mohmohcha]

It should be a n-well ring connected to the deep n-well, not just a single contact as in your layout.

In Cadence, I remember there is a switch in the parameter file to turn on the extraction of the well diode, you don't need to add the diodes on your schematics if the switch is not on (default setting off).

 

[mahdiiust]

Thank you very much!
It works!
but how can I draw n-well ring? I use M1_NWELL contact. but it has several DRC error.

 

[mohmohcha]

The layout looks good, not sure what drc errors you see.

 

[mahdiiust]

The layout looks good, not sure what drc errors you see.

This is DRC error.

 

[mohmohcha]

Should be easy to fix them, check the rules provided by the vendors.

Good luck.