Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
if the netlist generated from synthesis or P&R tools, that means pure logic circuits, it's no meaning for spice simulation with these circuits, just use HDL simulator with the back annotated netlist, it's accurate in timimg. but if you want got the power / IR drop data, you can use powermill / railmill.
it wil be so slow that you cannot accept it,if you do the transistorlevel simluation,maybe you can use star_sim oor timmill to do that,but I don't think it significative ,because you cannot optimize it effectivly through the edatools.You have to modify it by hand