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how to use netlist of synthesis?

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Full Member level 4
Dec 13, 2002
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I have read a file,it say when after synthesis can use spice to simiulate
the netlist,but i don't how to do it.please tell me.
have a nice day!

I think you make a mistake. The netlist produced by synthesis can't be simulated by spice. The netlist have to be p&r and after that can be spiced.

Some "faster" spice simulater can read Verilog netlist,
such as timemill. Of course, it needs spice model
of your cell library....

Hi, ttspice
I think even if timemill can spice netlist file generated by synthesis , But I think it 's not worth to do that. I think netlist generated by p&r tools can be fast spiced more accurately.

if the netlist generated from synthesis or P&R tools, that means pure logic circuits, it's no meaning for spice simulation with these circuits, just use HDL simulator with the back annotated netlist, it's accurate in timimg. but if you want got the power / IR drop data, you can use powermill / railmill.

it wil be so slow that you cannot accept it,if you do the transistorlevel simluation,maybe you can use star_sim oor timmill to do that,but I don't think it significative ,because you cannot optimize it effectivly through the edatools.You have to modify it by hand

most "mix-mode" simulator can run hdl and spice simultaneously,
and keep the advantage of hdl, there is a good tool call "smash".
try it...

smash is best than Hspice?

xtecer said:
smash is best than Hspice?

smash is a mix-mode simulator.
it can simulate with spice netlist, vhdl, verilog, and c.
hspice is only for spice netlist.

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