How to use mutiplied transistors in layout XL?

[mtwieg]

I'm just getting into layout using the UMC 65nm PDK, and I need some matched pairs and wanted to do common centroid layouts of transistors. However if I set m>1 in the schematic, then use "create from source" in layout XL on that component, it only creates a single instance of the device. I'm unable to generate the other m-1 parts of the m>1 transistor. I've found a few layout tutorials using umc pdks, but none of them cover m>1 devices, so I'm unsure how to proceed (except for actually putting multiple copies of the devices with m=1 each in the schematic, which would be quite tedious).

So how would an expert do this? Is virtuoso able to automatically create multiplied transistors? It would be really nice if it could do so in arrays with interconnects. Doubly awesome would be automatic common centroid layout of separate transistors. Does such functionality exist?

 

[erikl]

Is virtuoso able to automatically create multiplied transistors?

Until now I haven't seen this capability. AFAIR, it works with fingers, however.

It would be really nice if it could do so in arrays with interconnects.

Did you try arrays? I mean from the schematic array<1:m> representation?

Doubly awesome would be automatic common centroid layout of separate transistors. Does such functionality exist?

Not in Layout XL, I think. Always had to layout and connect my common centroid design parts myself :-(

 

[mtwieg]

Until now I haven't seen this capability. AFAIR, it works with fingers, however.

Yes, fingering works fine, thankfully.

Did you try arrays? I mean from the schematic array<1:m> representation?

Not sure I follow. Do you mean creating several devices using the copy tool with columns and rows? I'm hoping that there is a way to do this without needing multiple symbols in the layout.

Not in Layout XL, I think. Always had to layout and connect my common centroid design parts myself :-(

I'm honestly a bit shocked at this. Certainly career designers must have some tools for it, though I doubt they'll be sharing...

In any case it at least makes me feel better that someone with expertise can confirm that I'm going to be wasting huge amounts of time in my layout because I missed the "create perfect array" button.

 

[erikl]

Did you try arrays? I mean from the schematic array<1:m> representation?

Not sure I follow. Do you mean creating several devices using the copy tool with columns and rows? I'm hoping that there is a way to do this without needing multiple symbols in the layout.

What I mean is: if you have a transistor<1:8> in schematic, does Layout XL (at least) succeed in creating 8 equal transistors? I don't remember, but I'd think so.

I'm honestly a bit shocked at this. Certainly career designers must have some tools for it, though I doubt they'll be sharing...

May be you can buy additional skill tools: have a look .

In any case it at least makes me feel better that someone with expertise can confirm that I'm going to be wasting huge amounts of time in my layout because I missed the "create perfect array" button.

You really can't expect it for those few bucks ;-) . The SKILLCAD people just need a few more ...

 

[dick_freebird]

A "m" (or "nf") param ought to generate a single multistripe
transistor. An iterated instance (e.g. M0<15:0>) ought to
generate 16 single transistors of whatever asserted finger
count. The LVS will permute-parallel what it finds to be truly
parallel in the netlist and hopefully figure / check the ad, as,
pd, ps values against those assigned in the schematic.

 

[rangermad]

Need to be careful though because M0<15:0> does not equal M0 with nf=16.

 

[mtwieg]

I was unaware of instance arrays, now I see what you mean. Yes, if I name the instance "name<m:1>" in the schematic, then generate it in the layout, it will create a row of the devices with some arbitrary spacings (hopefully the DRC minimum), and I can place them as a group. No interconnects are generated automatically. Strangely, if I make a two dimensional instance array, the result in the layout is still a one dimensional array, with a number of devices equal to the smallest dimension.

Somewhat helpful, but not really useful for common centroids. Is there a way to change the spacing of the arrays when created in the layout? If I could double the spacings in one dimension, then I could interleave two different arrays, which would be fairly useful. But I don't see anything in the "create from source" dialog that allows this.

 

[erikl]

... Is there a way to change the spacing of the arrays when created in the layout? If I could double the spacings in one dimension, then I could interleave two different arrays, which would be fairly useful. But I don't see anything in the "create from source" dialog that allows this.

From the old Virtuoso 5.1.41 times I remember there was an option to set the spacing between the individual array cells. Before you click "create from source", I think.

 

[dick_freebird]

I would just use the placement as a starting point, I never have
seen auto-gen'd devices come out anywhere close to where my
eye wants them to be.

 

[jatram]

yes you can change the spacing while Generating from source by updating the value of the field "Minimum Seperation" in Position setting in Generate Tab of the Layout Generation form. The default is 1um and you can choose how much you wish.

 

[dick_freebird]

In the placed array you should find editable deltaX, deltaY
properties.