Feb 22, 2016 #1 U u24c02 Advanced Member level 1 Joined May 8, 2012 Messages 404 Helped 2 Reputation 4 Reaction score 2 Trophy points 1,298 Activity points 4,101 Dear all, I'm trying to excercise with some systemverilog example on www.testbench.in of swith example. But I'm confused in here. Code: output_interface output_intf[4](clock); testcase TC(mem_intf, input_intf, output_intf); program testcase (..., output_interface.OP output_intf[4]); Versus Code: output_interface output_intf[4](clock); testcase TC(mem_intf, input_intf, output_intf[4]); program testcase (..., output_interface.OP output_intf[4]); I'm confused that I think it must be like this. testcase TC(mem_intf, input_intf, output_intf[4]); not testcase TC(mem_intf, input_intf, output_intf); Would you let me know how to use multiple port?
Dear all, I'm trying to excercise with some systemverilog example on www.testbench.in of swith example. But I'm confused in here. Code: output_interface output_intf[4](clock); testcase TC(mem_intf, input_intf, output_intf); program testcase (..., output_interface.OP output_intf[4]); Versus Code: output_interface output_intf[4](clock); testcase TC(mem_intf, input_intf, output_intf[4]); program testcase (..., output_interface.OP output_intf[4]); I'm confused that I think it must be like this. testcase TC(mem_intf, input_intf, output_intf[4]); not testcase TC(mem_intf, input_intf, output_intf); Would you let me know how to use multiple port?