I have read some information about LUT in FPGA, but I wonder that How to use LUT in Verilog program for Altera chip.
Anybody can load a simple program use LUT by verilog for me and compare the perfomance with the program without using LUT ? I am confusing about LUT
definition and can not make it clearly.
In addition, I try to design a fast multiplier using ROM, anybody can share some information or give me some recommendation ?
Hi, I think you don't need care about that. All the things that you do is write rtl code or drawing schematic. How to match you code with FPGA's LUT is FPGA tools must to do. Synthesis, P&R etc.
Hi, I think you don't need care about that. All the things that you do is write rtl code or drawing schematic. How to match you code with FPGA's LUT is FPGA tools must to do. Synthesis, P&R etc.
Thank you but I still wonder about LUT because when I write RTL code and simulation it with other type of FPGA. The perfomance is different and I want to explain it, I think that performance depends on size of LUT in each FPGA chip. Because I try to write some FFT code and design FIR so I have to learn about the structure of LUT to optimize the delay time.
I think that it don't consider it for simulation tool can generate corresponding result.
you can try to synthesis a VHDL program, and you can find the usage about LUT.