Sep 25, 2012 #1 H hari10 Newbie level 4 Joined Sep 25, 2012 Messages 6 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,315 hi..i want to use fpga memory .......is there any command for doing this..if yes plz tell me........because i dont want to use register array in my program.... thnx in advance.......
hi..i want to use fpga memory .......is there any command for doing this..if yes plz tell me........because i dont want to use register array in my program.... thnx in advance.......
Sep 25, 2012 #2 S soloktanjung Full Member level 6 Joined Nov 20, 2006 Messages 364 Helped 51 Reputation 100 Reaction score 43 Trophy points 1,308 Location nowhere Activity points 3,194 Use the block RAM by instantiating it in the VHDL code: Code VHDL - [expand]1 2 3 4 5 6 7 8 9 10 11 12 13 -- Block SelectRAM Instantiation U_RAMB16_S36: RAMB16_S36 port map ( DI => DATA_IN (31 downto 0), -- insert 32 bits data-in bus (<31 downto 0>) DIP => DATA_IN (35 downto 32), -- insert 4 bits parity data-in bus (or <35 downto 32>) ADDR => ADDRESS (8 downto 0), -- insert 9 bits address bus EN => ENABLE, -- insert enable signal WE => WRITE_EN, -- insert write enable signal SSR => INV_SET_RESET, -- insert set/reset signal CLK => CLK_BUFG, -- insert clock signal DO => DATA_OUT (31 downto 0), -- insert 32 bits data-out bus (<31 downto 0>) DOP => DATA_OUT (35 downto 32) -- insert 4 bits parity data-out bus (or <35 downto 32>) ); From https://www.es.ele.tue.nl/mininoc/doc/xapp463.pdf. Thanks.
Use the block RAM by instantiating it in the VHDL code: Code VHDL - [expand]1 2 3 4 5 6 7 8 9 10 11 12 13 -- Block SelectRAM Instantiation U_RAMB16_S36: RAMB16_S36 port map ( DI => DATA_IN (31 downto 0), -- insert 32 bits data-in bus (<31 downto 0>) DIP => DATA_IN (35 downto 32), -- insert 4 bits parity data-in bus (or <35 downto 32>) ADDR => ADDRESS (8 downto 0), -- insert 9 bits address bus EN => ENABLE, -- insert enable signal WE => WRITE_EN, -- insert write enable signal SSR => INV_SET_RESET, -- insert set/reset signal CLK => CLK_BUFG, -- insert clock signal DO => DATA_OUT (31 downto 0), -- insert 32 bits data-out bus (<31 downto 0>) DOP => DATA_OUT (35 downto 32) -- insert 4 bits parity data-out bus (or <35 downto 32>) ); From https://www.es.ele.tue.nl/mininoc/doc/xapp463.pdf. Thanks.
Sep 25, 2012 #3 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 Or follow the HDL coding guidelines for infering ram for you intended target manufacturer, without having to directly instantiate the rams. - - - Updated - - - hairo said: Use the block RAM by instantiating it in the VHDL code: From https://www.es.ele.tue.nl/mininoc/doc/xapp463.pdf. Thanks. Click to expand... That is a Xilinx component, so wont work in altera.
Or follow the HDL coding guidelines for infering ram for you intended target manufacturer, without having to directly instantiate the rams. - - - Updated - - - hairo said: Use the block RAM by instantiating it in the VHDL code: From https://www.es.ele.tue.nl/mininoc/doc/xapp463.pdf. Thanks. Click to expand... That is a Xilinx component, so wont work in altera.
Sep 26, 2012 #4 H hari10 Newbie level 4 Joined Sep 25, 2012 Messages 6 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,315 thanx.........