how to use Digital Clock Manager of FPGA

[moonnightingale]

the manual of my spatran 3E fpga kit says

Alternatively, use
the FPGA’s Digital Clock Manager (DCM) to generate or synthesize other frequencies from
the on-board 50 MHz oscillator.

Lets suppose i want to ues clock of 30 MHZ. HOW CAN I DO IT.

 

[pratheek]

easy way is to use xilinx coregenrator , coregen tool to create a pll divided clock from the 50 MHz crystal on borad.
pls go through the coregen help; its simple and easy to use

 

[moonnightingale]

I am using free version of ISE webpack 12.3
fromwhere i can launch coregenerator

 

[pratheek]

hi,
from project navigator, add a new file --> goto ip type a name and click nest, this will open up a screen of coregen luisting all core availabe for the device..
some of the cores are free and some are time bound for say 4 hours. DCM is free unless there are other cores which are really costly.
onces in this tool its self explanatory u can use xilinx site or ise help , post a qurry if not working i can send screen shots

 

[bigdogguru]

Hi,

Here is an Xilinx ISE 12.x tutorial with step-by-step instructions on how to generate a DCM as well as many other interesting tips.

Hope this helps in your endeavor!

 

[moonnightingale]

Thanks a lot bigdogguru.
Can i make clock of any frequency by DCM.
my board is spatran 3E, its built in clock is 50 MHZ.
Can i make 40, 38 or any MHZ clock
Can i also make clock higher than 50 MHZ, i mean 60 MHZ by DCM? what is upper limit

What is DCM deskew

 

[mrflibble]

Check Using Digital Clock Managers on page 65. And also see Creating a DCM Module on page 64.

That contains all the answers to all your questions (well, in this thread)!!! Happy RTFM experience!

 

[bigdogguru]

Hi,

Here is the "Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs" app note, which I thought I uploaded earlier, apparently not. It goes into great detail concerning implementation of DCMs on Spartan 3E, limitations, features and capabilities.

It should provide the answers your looking for.

Ciao

 

[mrflibble]

Here is the "Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs" app note, which I thought I uploaded earlier, apparently not. It goes into great detail concerning implementation of DCMs on Spartan 3E, limitations, features and capabilities.

As per the spartan-3E appnotes page.

01/05/2006 XAPP462 - Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs(PDF, ver 1.1, 796 KB )
For the latest version of this application note, see the DCM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

Which is why I previously linked to ug311, page 65. But like you said, it contains all the answers to the OP's questions regarding DCMs.

Hope moonnightingale gets his DCM running.