How to use CPLD with Xilinx FPGA

[kannan.tulasi]

Hi,

I am using Spartan 3e with XC3S500E fpga and XC2C64A CPLD. I want to load my design in CPLD and want to access it through FPGA. Since the CPLD seems to be not accessible individually. More than that my design size is large i want to use it with share the resource of CPLD.

can anyone help me?

Thank you...

 

[kel8157]

Normally people only use FPGA to implement major part of the design, CPLD is only used for interfaces to some hardwares.
It could be the CPLD is used to program the FPGA, so if you erased the CPLD(or loaded your design in the CPLD), then you will find difficulty load bit-stream from PROM to FPGA.

 

[khamitkar.ravikant]

use u r normal ise project navigator as usual but instead of device spartan3e family use cool runnerII as device family and then select xc2c64a in that.
then next u need to do is read the manual of s3e kit and find packaging of device and speed grade then next write u rprogram and other synthesis and implementation as per requirement also generate the program (download file) at the end.
now u need to do some study of kit on which there are different modes that u can select with jumpers m0 m1 m2 so that u can program cpld as per u r requirements.

 

[kannan.tulasi]

Hi Mr.Ravi

Thanks for your reply and suggestions..

I have once more query. In the assign configuration window I saw that there is 33 user I/O's available for XC2C64A. But how can I use those user I/O's, like used in FPGA?

Is it possible to directly access the CPLD user I/O's? Otherwise I have access it through FPGA?

My wich is to utilise the CPLD resource along with FPGA. Do not want to use/leave that alone. IS there any way?

Thank you.