I am really sorry, but I don't get what is meant by hard instance here. I have come across this term in some of the other forum posts as well, but it wasn't exactly mentioned what is meant by it. As I had mentioned before I have the .lib, .v files, how should I generate the hard instance out of these files?
I did trying specifying the SRAM instance in the following manner:
SRAM_32x1024_1rw mem(.clk0(clk0), .din0(din0), .dout0(dout0), .addr0(addr0), .csb0(csb0), .web0(web0));
I got the error message that mem is not a register, and I was getting a segmentation fault. After which I commented out all the read-write logic from the verilog code corresponding to the SRAM. Now the code was able to synthesize and I can see in the cell_usage report that the SRAM library is being used. But in the timing report, I can't see any timing arcs from any of the SRAM pins/ports. Now, I am confused about how will the design ensure to which location to read and write from and when? Am I doing it wrong?
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