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How to understand this sentence?

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bittware

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"there is less charge injection at a point of lower signal impedance"

the sentence appears in "the art of electronics" pg151 where discussing the proper FET switch position.

Anyone could explain it?

Thanks in advance!
 

Kral

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bittware,
They are talking about the capacitively coupled spike that is coupled into the "On" channel when a FET switches. Let Cs represent the equivalent capacitance between the FET control input voltage and the "On" channel. If the FET source is connected to the input (presumabllya low impedance Rs), then the voltage divider formed by Cs and Rs will attenuate the voltage spike.
Regards,
Kral
 

bittware

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Kral said:
bittware,
They are talking about the capacitively coupled spike that is coupled into the "On" channel when a FET switches. Let Cs represent the equivalent capacitance between the FET control input voltage and the "On" channel. If the FET source is connected to the input (presumabllya low impedance Rs), then the voltage divider formed by Cs and Rs will attenuate the voltage spike.
Regards,
Kral
Hi Kral,
Thanks for your reply.
But your explanation has noting to do with why lower input source impedance results in less coupling voltage.
Could you clarify it in formula?

Thanks,
bittware
 

libinphy

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hi:
you can learn it from the physics of semiconductor or the physics of semiconductor device.
 

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