How to understand this Asynchronous SAR ADC

wjxcom

Full Member level 5
Joined
Sep 7, 2005
Messages
281
Helped
4
Reputation
8
Reaction score
3
Trophy points
1,298
Activity points
3,840
Hi all: look at this interesting sar topology, which still uses redundancy technology and uses Main-Sub-DAC Array. In this capacitor array, the highest and second highest bits are "taken" from 22 unit capacitors, but only 11 unit capacitors are used in the high position capacitor array, and the rest may be placed in the LSB capacitor array, but there are only 4 (or 3?) redundancy in the LSB array instead of 11. I don't understand, how do you put redundancy in the MSB array into the LSB array? This topology comes from Low-Power High-Performance SAR ADC with Redundancy and Digital Background Calibration,the author is Albert Hsu Ting Chang

Please help me, thax!!!
 

Attachments

  • 1700790447793.png
    67.9 KB · Views: 62

Similar threads

Cookies are required to use this site. You must accept them to continue using the site. Learn more…