maxfli
Newbie level 2
verilog trigger
Hi all,
I want to design a signal that can trigger by using rising edge and falling edge by
using Verilog and download it into FPGA by using Quartus.
for example:
//--------------------------------------------------------
always_ff @(posedge DF_CLK, posedge seen)
begin
if (seen == '1)
externalclk= '0;
else
externalclk= '1;
end
//--------------------------------------------------------
is it possible change the trigger by both rising and falling edge??
thank you so much
Hi all,
I want to design a signal that can trigger by using rising edge and falling edge by
using Verilog and download it into FPGA by using Quartus.
for example:
//--------------------------------------------------------
always_ff @(posedge DF_CLK, posedge seen)
begin
if (seen == '1)
externalclk= '0;
else
externalclk= '1;
end
//--------------------------------------------------------
is it possible change the trigger by both rising and falling edge??
thank you so much