How to trigger rising and falling by using Verilog?

[maxfli]

verilog trigger

Hi all,

I want to design a signal that can trigger by using rising edge and falling edge by

using Verilog and download it into FPGA by using Quartus.

for example:
//--------------------------------------------------------
always_ff @(posedge DF_CLK, posedge seen)
begin
if (seen == '1)
externalclk= '0;
else
externalclk= '1;
end
//--------------------------------------------------------

is it possible change the trigger by both rising and falling edge??

thank you so much

 

[RBB]

rising edge verilog

Yes this is possible. The seen signal will be synthesized as a asynchronous reset signal asserted high, while the DF_CLK will be synthesized as a positive edge triggered clock.