I want to transport the synthesized design to Cadence Composer. If I save the Synopsis design as verilog format and import in Cadence, the standard cell symbols will become default rectangle symbols other than those provided by the foundry. If I save the Synopsis design as EDIF, I get a error message which says, "The meter scales in libraries 'generic.sdb' and 'stdcell' aren't equal. (EDFO-2)"
I am newbie in digital design. Any friends can help me? Thanks in advance.
I met those problems once years ago. It was a lib's problem. You migh want to check your lib... tim, cel, frame for synopsys, but lef, tlf, def for Cadence...
This problem is solved now. Put the synthesized verilog netlist and the components definition file provide by foundry in the form entry "Files to be imported", and add the symbol library name to the form entry "Referenced Libraries".