How to transport a design from Synopsis to Cadence?

[Hughes]

import stdcell cadence

I want to transport the synthesized design to Cadence Composer. If I save the Synopsis design as verilog format and import in Cadence, the standard cell symbols will become default rectangle symbols other than those provided by the foundry. If I save the Synopsis design as EDIF, I get a error message which says, "The meter scales in libraries 'generic.sdb' and 'stdcell' aren't equal. (EDFO-2)"

I am newbie in digital design. Any friends can help me? Thanks in advance.

 

[linuxluo]

hi,
I think verilog netlist import to cadence is OK. the symbol error is becoz you dont set the correct symbol lib in you ambit environment

 

[zyphor]

I agree. Netlist & .lib file are imdependent to the tools.

 

[Hughes]

hi,
I think verilog netlist import to cadence is OK. the symbol error is becoz you dont set the correct symbol lib in you ambit environment

I agree. Netlist & .lib file are imdependent to the tools.

I don't doubt the ability of the tools. I just don't know how to use the tools.

 

[sandusty]

I met those problems once years ago. It was a lib's problem. You migh want to check your lib... tim, cel, frame for synopsys, but lef, tlf, def for Cadence...

 

[Hughes]

This problem is solved now. Put the synthesized verilog netlist and the components definition file provide by foundry in the form entry "Files to be imported", and add the symbol library name to the form entry "Referenced Libraries".

 

[CatKing]

check the "Cadence-Synopsys Interface" (CSI) in the manual.

 

[asic8@lycos.com]

see attached cadence to synopsys interface reference manual

 

[spauls]

Import design and SDC (Generad by DC) to Cadence,
it will except.

 

[pamulurureddy]

You migh want to check your lib... tim, cel, frame for synopsys, but lef, tlf, def for Cadence...

i am generating standard cell with difft ext with respect to the customer

 

[sam3001]

Thanks

 

[andy2000a]

cadence composer can verilog In ..but if netlist too complex or composer GRID too large ..

verilogIN have bug on it .. some net will "broken" and have different netname (even the same net)

it is bug .. early version composer BUG

by the way , Have other scehmatic tool can verilog-IN ??