How to translate complex algorithms to RTL

[bigrice911]

We need to do a project to make a voice recognition chip, now we have a verified algortihm and some other related ones. What we should do now is to translate these complex algorithms to RTL(Verilog discription). The algorithms may come from DSP chip which is based on C or ASM programming. I got no experience to do this job, can anyone explain me the basic methodology or recommand some resource or cases to study?

I am familiar with RTL design(ASIC and FPGA), but I have never got any idea with DSP algorithm.

 

[Ahmed Mukhtar]

View Cadence Design Systems Website you will Find a completed integrated Design Methodology, that Satisfy your needs, base on Cadence EDA tools.

 

[stormwolf]

Maybe you need try coware.

 

[zhangpengyu]

Divide then occupy!

 

[omara007]

You first need to receive some documentation about the algorithm you are going to implement. Study them well and if you already have a code (C implemented on DSP), you should view its documentation. Then try to take the already implemented-in-DSP blocks and start re-implementing them as RTL. This may imply moving from a certain level of abstraction to another lower level of abstraction. for example, C doesn't care about clocks, while RTL cares. C doesn't take into concisderation synchronization, RTL cares. C doesn't interact much with hardware, while RTL is hardware.
You need also to partition your system , maybe you will still need a processing to be available in your design. After partitioning your system, go for partitioning your blocks to sub-blocks and so on, till you reach a certain level of abstraction where you feel you are comfortable with describing it in RTL. At this moment start writing your State Machines.

Hope this helped.

 

[wwfhm2002]

Accelchip can help you translate .m file to .v file.