# How to transfer a value of an output from DUT to test bench?

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#### ragulto516

##### Newbie level 2
Hi,

Would like to ask how to transfer a value of an output from DUT to test bench?

I have the following code:

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module my_mod(a, b);
input a;
output b;

assign b = a;
endmodule

module my_mod_tst();
reg x;
wire y;
reg z;

my_mod_tst mmt(x, y);

initial begin
x = 1;
z = y;

if (z == 1)
display$("Value of z is %d", z); end endmodule But it does not work. Last edited by a moderator: #### dave_59 ##### Advanced Member level 3 It will help others and probably yourself if you explain what "does not work" means. What happens? What did you expect to happen? Look at the log file carefully. FvM ### FvM Points: 2 Helpful Answer Positive Rating #### Ashish Agrawal ##### Member level 3 my_mod_tst mmt(x, y); Your Instantiation is wrong. Instead of writing my_mod_tst write my_mod (Module to be instantiated, not the test bench). ragulto516 ### ragulto516 Points: 2 Helpful Answer Positive Rating #### sharath666 ##### Advanced Member level 2 You have not instantiated ur RTL in the first place. Check out the syntax for instantiating... #### ragulto516 ##### Newbie level 2 Hi, Yes, apologies, I have instantiated the module incorrectly and here is the rewrite. Code: module my_mod(a, b); input a; output b; assign b = a; endmodule module my_mod_tst(); reg x; wire y; reg z; my_mod mm(x, y); initial begin x = 1; z = y; if (z == 1)$display("Value of z is %d", z);
end
endmodule

But after running it in simulator the test bench variable z becomes equal to 1'bx. Is there a way how to transfer the value from module under test to test bench correctly? Thanks.

#### sharath666

The statement z=y and the display statement should be in always blocks and not in the initial block.

#### dave_59

This is a simulation race condition. You are writing variable x and reading wire y with no delay in between. The initial block and continuous assignment are two independent processes, and without any delays or wait statements in the initial block, there is no guarantee that the continuous assignment in my_mod will execute in between the write and the read. Different version of Modelsim/Questa produce different results.

Generally, you write to your DUT inputs at one time, and read your DUT outputs at another time.

Code:
module my_mod(input a, output b); // preferred way to write your ports
assign b = a;
endmodule

module my_mod_tst();
reg x;
wire y;
reg z;

my_mod mmt(x, y);

initial begin
x = 1;
@y // or #1
z = y;
if (z == 1)
\$display("Value of z is %d", z);
end
endmodule
In most cases, you have a clock and can apply stimulus on a clock edge with a non-blocking assignment, and read the stimulus from the previous clock cycle at the same time

ragulto516

Points: 2