Again..stability is not tolerance.
tolerance is error at 25'C
stability is VS temp. + aging for all crystals !!
Reduce series R 300k to 10k
The 1uW power limit is actually done by cap shunt current and high input impedance and feedback R, not output impedance.
The series R acts as LPF for overtones and you may be attenuating fundamental.(guess)
300k*22pF= 6.6ns. (guess not)
Consider your CMOS inverter 74HCxx or 74LVCxx has a blown input from ESD.
Measure Vdc of output and input with 10M probe. Now input is attenuated 50% and duty cycle changes on output.
Next change 10M to 1M and repeat probe above. If Vin is not near Vcc/2, is is a dead gate. Vin must Equal Vout avg with 50% duty cycle when operating normal since chip gain is >10x for non buffered and >1000x for (3 stage) buffered and you have a negative feedback linear amp phase shift oscillator.
It won't work on TTL directly (74LSxx) due to IIL input low current, Ensure Vcc decoupling cap near Chip
If all else fails , you have blown your first microslice MEMs tuning fork rated for 1uW max due to invalid 74LS application or ESD. congrats.