During implementation place and route works out interconnectivity to meet timing.
You can constrain the tool to PAR items closer.
However if you want to generate a test for components used in
vivado you can do
Code:
launch_modelsim -mode [ behavioral | post_synthesis | post_implementation ] -type [ functional | timing ]
Where
-mode Specifies either a behavioral simulation of the HDL design sources to verify syntax and confirm
that the design performs as intended, a functional or timing simulation of the post-synthesis
netlist, or a functional or timing simulation of the post implementation design to verify circuit
operation after place and route. The default mode is behavioral.
-type [ functional | timing ] - (Optional) Cannot be used with -mode behavioral. Specifies
functional simulation of just the netlist, or timing simulation of the netlist and SDF file. The
default is functional. Post-synthesis timing simulation uses SDF component delays from the
synth_design command. Post-implementation timing simulation uses SDF delays from the
place_design and route_design commands.
Note Do not use -type with -mode behavioral, or the tool will return an error.