How to test different values of generic (generic map) in vhdl all in one testbench -
Hi
VHDL-I was wondering how to test different values/conditions of generics (generic map) all in one testbench without making multiple testbenches with different generic conditions...
Re: How to test different values of generic (generic map) in vhdl all in one testben
Your testbenches can also have generics. In modelsim, you can pass generics using -g. This only works for basic types.
Code:
vsim -gANY_NAME_HERE=5
There are other options as well. For example, within a function in a package you can convert a test case number into a more complex type. I think you can also have functions that read complex test cases from a file as well.
Re: How to test different values of generic (generic map) in vhdl all in one testben
You can't change generics during run time, so the only options are to either
1) run the test bench multiple times using scripting
2) instantiate the dut multiple times in a single testbench.
Usually, people use the first method to keep single cases separate and allow easier debugging
Re: How to test different values of generic (generic map) in vhdl all in one testben
Thanks everyone. I was wondering if anyone can share an example here passing on generics with are std_logic_vectors. Also then how to use assert statements then as it will be different for different generic parameters.
Thanks very much. I did exactly the same but was not able to make it work. Anyway you very also suggesting that one can use the functions to chane the generics many time in a single test bench. Can I have an example for that? Cheers
Thanks very much. I did exactly the same but was not able to make it work. Anyway you very also suggesting that one can use the functions to chane the generics many time in a single test bench. Can I have an example for that? Cheers
You must start the simulator once for every combination of generics, but you can supply them from the command line so the design and test bench files can stay unchanged.