Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to test decoder 2 to 4

Status
Not open for further replies.

boyzzun

Junior Member level 1
Junior Member level 1
Joined
Mar 16, 2012
Messages
18
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,531
i have a homework that i have to code the decoder 2_4 like ic 74139,then i found the code for this
Code:
library ieee ;
use ieee.std_logic_1164.ALL;
entity decoder_2_4 is
port( a : in std_logic_vector(1 downto 0);
      en : in std_logic;
	  y : out std_logic_vector(3 downto 0)
	  );
end entity;
architecture cond_arch of decoder_2_4 is

begin
	
    y <= "0000" when (en='0') else
	     "0001" when (a="00") else
		 "0010" when (a="01") else
		 "0100" when (a="10") else
		 "1000";
end cond_arch;
but i don't know the code test for this,could you help me
 

first of all, I suggest writing a testbench.
 

a testbench is just a VHDL file instantiating your unit under test. The inputs are just generated in the testbench, something like this:

input <= '1', '0' after 1 us, '1' after 2us;

or you can use wait statements inside a process.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top