how to sythesize design with `define?

[Natwar Agrawal]

Hi,

I am using `define MEM_RST in the memory which basically use reset if MEM_RST is defined. While compiling using design compiler I defined MEM_RST in the top file only . But it does take into effect. Is there a way I can do systhesis without defining MEM_RST for each file where it is used.

THanks,
Natwar

 

[yx.yang]

If you use synopsys, you may have the following choice:
1): use analyze and elaborate to read in the design, when do "analyze", you can have the -define option, and define your "MEM_RST"
2): use read_verilog command read in the design, and write all your defines in a file: prj_define.v, list prj_define.v at the first line of you filelist.
3): And define is always globle, if you write it outside of "module / endmodule". So you can write `define MEM_RST on the first file you read in. (this is not a good way, why?)

 

[rca]

this memory element isn't replace by a macro view (liberty) during the synthesis?