srpatel9
Junior Member level 3

Hi all,
Does anyone have any idea how to synthesize a generated clock?.
What i have is CLK2 and CLK1.
Clk1 is global clock.
Clk2 is generated using CMOS logic. Inputs of this CMOS logic comes from gates that use CLK1 as their clock.
What I am trying to build is a self timed circuit. Level-2 waits for Level-1 to complete. CMOS logic in between behaves like a clock generator for level2.
I will be really appreciate if you can give me some idea how to
synthesize this in Cadence RTL complier or in DC with commands that can be feed to RTL complier.
Thanks.
Does anyone have any idea how to synthesize a generated clock?.
What i have is CLK2 and CLK1.
Clk1 is global clock.
Clk2 is generated using CMOS logic. Inputs of this CMOS logic comes from gates that use CLK1 as their clock.
What I am trying to build is a self timed circuit. Level-2 waits for Level-1 to complete. CMOS logic in between behaves like a clock generator for level2.
I will be really appreciate if you can give me some idea how to
synthesize this in Cadence RTL complier or in DC with commands that can be feed to RTL complier.
Thanks.