how to synthesize a shifter in FPGA Block_ram ?

[Matrix_YL]

HI all
I waste too much LUTS in my chip! so I want to use my block_ram resource.Is there any ways to synthesize a shifter in BlockRam of XILINX's FPGA!
how set my EDA tools (Synplify 7.5) or add some attributes to complete it!

my device xcv50bg256-6.

verilog and vhdl are all best needed !

thank you !

 

[echo47]

See page 27 of App Note 463:
https://www.xilinx.com/bvdocs/appnotes/xapp463.pdf

Or you can use coregen to create one. The current version is called "RAM-based Shift Register 8.0".
**broken link removed**

 

[mrnoone]

////////////
module shifter_main(Q,A,C0,C1,C2,Cin,Cout);
input [7:0] A;
input C0,C1,C2,Cin;
output [7:0] Q;
output Cout;
reg [1:0]S;
always @ (C0 or C1 or C2)
if(C0) S=2'b00;
else if(C1) S=2'b01;
else if(C2) S=2'b10;
else S=2'b11;
shifter cct(Q,S,A,Cin,Cout);
end module





//////////////
module Barrel_shifter_main(A,C0,C1,C2,C3,Q);
input [7:0]A;
input C0,C1,C2,C3;
output [7:0]Q;
reg [2:0]S;
always @ (C0 or C1 or C2 or C3)
if(C0) S=3'b001;
else if(C1) S=3'b011;
else if(C2) S=3'b101;
else if(C3) S=3'b111;
else S=3'b000;
barrel_shifter shfter(A,S,Q);
end module
//

The code for the 4x1 MUX used in the Shifter;
module mux(y,d0,d1,d2,d3,s);
input d3,d2,d1,d0;
input [1:0]s;
output y;
reg y;
always @ (d0 or d1 or d2 or d3 or s)
case (s)
2'b00:y=d0;
2'b01:y=d1;
2'b10:y=d2;
2'b11:y=d3;
endcase
end module
//




module mux8x1(y,d0,d1,d2,d3,d4,d5,d6,d7,s);
input d0,d1,d2,d3,d4,d5,d6,d7;
input [2:0] s;
output y;
reg y;
always @(d0 or d1 or d2 or d3 or d4 or d5 or d6 or d7 or s)
case (s)
3'b000:y=d0;
3'b001:y=d1;
3'b010:y=d2;
3'b011:y=d3;
3'b100:y=d4;
3'b101:y=d5;
3'b110:y=d6;
3'b111:y=d7;
endcase
end module

//

module shifter(Q,S,A,Cin,Cout);
input [7:0] A;
input [1:0]S;
input Cin;
output [7:0] Q;
output Cout;
parameter d=1'b0;
reg Cout;
mux mux1(Q[7],A[7],Cin,A[6],d,S);
mux mux2(Q[6],A[6],A[7],A[5],d,S);
mux mux3(Q[5],A[5],A[6],A[4],d,S);
mux mux4(Q[4],A[4],A[5],A[3],d,S);
mux mux5(Q[3],A[3],A[4],A[2],d,S);
mux mux6(Q[2],A[2],A[3],A[1],d,S);
mux mux7(Q[1],A[1],A[2],A[0],d,S);
mux mux8(Q[0],A[0],A[1],Cin,d,S);
always @ (A or S)
case (S)
2'b00: Cout=0;
2'b01: Cout=A[0];
2'b10: Cout=A[7];
2'b11: Cout=0;
endcase
endmodule
//



//The code for the rotator;
module barrel_shifter(A,S,Q);
input [7:0]A;
input [2:0]S;
output [7:0]Q;
parameter d=1'b0;
mux8x1 mux0(Q[7],d,A[6],A[5],A[4],A[3],A[2],A[1],A[0],S);
mux8x1 mux1(Q[6],d,A[5],A[4],A[3],A[2],A[1],A[0],A[7],S);


mux8x1 mux2(Q[5],d,A[4],A[3],A[2],A[1],A[0],A[7],A[6],S);
mux8x1 mux3(Q[4],d,A[3],A[2],A[1],A[0],A[7],A[6],A[5],S);
mux8x1 mux4(Q[3],d,A[2],A[1],A[0],A[7],A[6],A[5],A[4],S);
mux8x1 mux5(Q[2],d,A[1],A[0],A[7],A[6],A[5],A[4],A[3],S);
mux8x1 mux6(Q[1],d,A[0],A[7],A[6],A[5],A[4],A[3],A[2],S);
mux8x1 mux7(Q[0],d,A[7],A[6],A[5],A[4],A[3],A[2],A[1],S);
endmodule