how to synthesize a RTL that instantiates a memory block ?

[anilineda]

Hi,

I heard that , ASiC synthesizers wont synthesize a multi-dimensional arrays and considers them as a latch . In my case , genus taking more time during elaboration process for a small memory size .

i came to know that from internet that i have to infer memory files separetly but not in detail. please somebody guide me what actually it is , and give me some reference on this topic.

rightnow. i am commneting all the memory files and synthesizing , which is not correct . i know that

Regards,
Anil.

 

[ThisIsNotSam]

replace the memory by an empty verilog module. run synthesis. it will warn you about black boxes, but that's fine.

fule of thumb is don't ever synthesise memory, it's size, power, and performance will be way worse than a real SRAM memory block.

 

[anilineda]

Hi,
In which form this SRAM memory block available ?
how can i infer or instantiate in place of my ram . let it be " reg [7:0] ram [255:0] ; "?
give me the reference or example .

 

[ThisIsNotSam]

Hi,
In which form this SRAM memory block available ?
how can i infer or instantiate in place of my ram . let it be " reg [7:0] ram [255:0] ; "?
give me the reference or example .

do you have access to an SRAM compiler? it would generate .v, .lef, and .lib files for you.

 

[anilineda]

we don't have SRAM compiler tool, but sram libraries with the name temn28hpmhsram macros from imec via legal agreement in the past.
but how to make use of them, any genus commands or will genus automatically creates memories upon reading those sram macros.!!
I am very unclear on this.

 

[ThisIsNotSam]

we don't have SRAM compiler tool, but sram libraries with the name temn28hpmhsram macros from imec via legal agreement in the past.
but how to make use of them, any genus commands or will genus automatically creates memories upon reading those sram macros.!!
I am very unclear on this.

You are approaching this the wrong way. genus synthesises logic, not memories. genus will not instantiate, will not create, will not touch memories. memories should be instantiated by you, on your own verilog code.

 

[anilineda]

memories should be instantiated by you, on your own verilog code.

so, what should i do ? In the place/line of two-dimensional array declaration in the verilog code, i have to instantiate a particular sram cell so that my memory width, depth requirement and portlist(clka,clkb,dina,doutb,addra,addrb,we) of my memory design should match with the portlist of sram block . Am i correct ?

brief me.

 

[ThisIsNotSam]

so, what should i do ? In the place/line of two-dimensional array declaration in the verilog code, i have to instantiate a particular sram cell so that my memory width, depth requirement and portlist(clka,clkb,dina,doutb,addra,addrb,we) of my memory design should match with the portlist of sram block . Am i correct ?

brief me.

exactly like that.