[SOLVED] How to synthesis files taken from Vivado hls

[achaleus]

Hello all, I have done Synthesis, co-simulation and after test passed I exported to rtl(Ipxact) using Vivado HLS tool. I wanted to test on board which has virtex 6 fpga. So, I tried taking all rtl files and synthesizing on ISE 14.2 tool but unsuccesful. Vivado generated so many files, I don't know which file I have to add (syn or Impl) and libraries. I tried using both and I got errors as

files taken from synth:

cannot open file "/opt/Xilinx/14.2/ISE_DS/ISE/vhdl/xst/lin64/ieee_proposed/ieee_proposed.vdbl" for writing

files taken from impl: library errors like floating point v6_1 package.....

I am attaching codes in rar files with test bench( code is not optimized and performance doesn't matter as of now) I stuck here.. pls help

thanks,
vinay

 

[ads-ee]

If you are having problems compiling in ISE, compile it in Vivado and write out a netlist. The V7 and V6 have mostly the same library components. You might have to swap some that have changed names.

Also 14.2 is pretty old, are you using a Vivado that is equally old? Current versions are ISE 14.7 and Vivado 2014.2 (Vivado 2013.4 came out around the same time as ISE 14.7)

Regards

- - - Updated - - -

Realized you could probably generate an EDIF output from Vivado synthesis, so looked it up...

and found something that might help you out.
http://www.xilinx.com/support/answers/54074.html

 

[achaleus]

hey thanks for the reply I am using vivado 2012.2, I implemented this design( taking .zip file generated from Vivado hls) in vivado design suite but I unable to find EDIF.
How to generate this EDIF file so that I will use this design as black box in other designs.
we have V6 FPGA boards

 

[ads-ee]

You can load the design checkpoint for the synthesis using (you can also do it from the Vivado GUI):
read_checkpoint your_checkpoint_filename.dcp

Taken from UG835:
write_edif [-pblocks args] [-cell arg] [-force] [-security_mode arg]
[-quiet] [-verbose] file

The following example writes an EDIF netlist file for the whole design to the specified file name:
write_edif C:/Data/edifOut.edn

- - - Updated - - -

FYI, these are all Tcl console commands

 

[achaleus]

Thanks asd-ee, it helped