In my design ,there is a clock whose frequency can be 2M, 4M, .. 24M, how to synthesis it in design compiler to avoid setup and hold timing violation anytime.
if it is 2 asynchronous clocks, it is your design problem, in dc, you set_false_path.
if it is asynchronous clocks,let dc to process timing , same to one clock.
But there r some cases that a submodule use, say 12MHz clock and another submodule use, say 24Mhz clock? In this case, how should I synthesis my design? Thanks.
If you have a multi frequency system and the clocks are not related...not even multiples of each other....then things become quite difficult. If they are related then it becomes easier as you can define multi-cycle paths....
I have noticed that Ambit deals with multi frequency designs better than synopsys
If they're all synchonrous to each other, then the problem is not difficulte1) there're no multi-clock signals used by the other design using another clocks. In this case you can let the synthesis tool deal with the timing requirements. By default, if the signal generated by one clock is used by another clock's sampling, the timing should meet with the setup time requiremnts of the other clocks.(2) if the timing in the previous case cann't be met, then multi-clock (if sure of the number of the clocks required) or may be using set_false_path with handshake methods.
If there are multi-clock domains which means asynchronous to each other, then the problem is more difficult: (1) set_fasle_path using synchronizing circuits. (2) set_false_path using handshake methods just like Req and Ack handshakes
I ever designed my USBIF using multiple clock on one clock line. I set the timing constraint based on the max. speed freq. and there are no any unstable state occured. So you can try this rule in your desing.