How to synchronize inputs to FPGA with the Clock

[electromaniac]

synchronize fpga inputs

Hi all

Could you please help me

I am currently working in a project using Xilinx FPGA

the designed module have to take bits serially from outside the FPGA "external inputs"

The question now is how to make sure that this bit stream is synchronized with the clock of the block which comes from the internal clock of the FPGA

Does using Chipscope to drive inputs to FPGA solves this problem specially it has a core called VIO "virtual inpuy/output"

or shall I use an additional circuity to do this

Thank You

 

[rberek]

chipscope synchronize data

Well, you didn't tell us much about your bitstream.

You can synchronize it by taking the clock that is driving the device that is generating the bitstream and feeding it to your FPGA. Then you'd use a PLL or DCM to drive the circuitry that will latch your bitstream. This will also require you do make sure you distribute that clock carefully on the board to minimize skew.

Or, your bitstream might be source synchronous, where the clock is sent along with the data, and you would use that clock to sample the bitstream.

Or, if the bitstream's clock is not available, you have an asynchronous interface, and you'll have to use a much higher rate clock than the data was generated with, and sample the bitstream and detect the data edges and reconstruct the data yourself. RS232 works something like this.

Chipscope is a debugging tool for the lab, and is meant to be used with the Chipscope software.

r.b.

 

[omara007]

fpga dcm problem chipscope

Does using Chipscope to drive inputs to FPGA solves this problem specially it has a core called VIO "virtual inpuy/output"

Thank You

Yes. VIO core has synchronous Inputs and Outputs ..