xtcx
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hello friends!, In my application I have to select any 1 of 3 devices at the startup using user input. These 3 devices pin-outs will be connected to FPGA. I have to select only one of user choice. The pins are "clk, din, dout" pins for interface.3 devices are same....Now I have written a code to interface with this device. But my choice is to work with one depending upon user selection. I cannot use same clk for all devices. "clk" is in sensitivity list of the code. So should I hav to write 3 separate codes for 1 working device?.....I'm in need to reduce area and increase speed. So I tried to use a MUX concept to switch the clk,din,dout pins of the three to one, but Xilinx reports fatal:error only if I pass the clks of the three device into 1.....Basically i don't understand wheter clks can be switched or not?...I use "Rising_edge" of the device clk for operation.....Hence I cannot switch the desired clock for this purpose...Please help!.I have given a sample code.I pass the clock and other data pins to signal and then use that signal for device coding.I think the muxing of clock is the problem since it is again used in sensitivity list in next process.....If you could understand any please help.Thanks
Eg.,a
entity is
port(
clk1 : in std_logic;
din1 : in std_logic_vector;
dout1 : out std_logic_vector;
clk2 : in std_logic;
din2 : in std_logic_vector;
dout2 : out std_logic_vector;
clk3 : in std_logic;
din3 : in std_logic_vector;
dout3 : out std_logic_vector;
user_inpt : in std_logic_vector(1 downto 0)
);
.
.architecture .......
signal clk : std_logic;
signal din,dout : std_logiv-vector(7 downto 0) ;
.
..
\\-----mux for selecting the device for use ------\\
Process(clk1,clk2,clk3)
Begin
case user_input is
when "01" =>
clk <= clk1;
din <= din1;
dout1 <= dout;
when "10" =>
clk <= clk1;
din <= din1;
dout1 <= dout;
when "11" =>
clk <= clk1;
din <= din1;
dout1 <= dout;
when others =>
clk <= '0';
din <= (others => '0');
dout <= (others => '0');
end case;
end process
--------------------------------
Process(clk)
begin
if rising-edge(clk) then
.
.
.
.\\ --- reading and writing data from\to device----\\
end process;
Eg.,a
entity is
port(
clk1 : in std_logic;
din1 : in std_logic_vector;
dout1 : out std_logic_vector;
clk2 : in std_logic;
din2 : in std_logic_vector;
dout2 : out std_logic_vector;
clk3 : in std_logic;
din3 : in std_logic_vector;
dout3 : out std_logic_vector;
user_inpt : in std_logic_vector(1 downto 0)
);
.
.architecture .......
signal clk : std_logic;
signal din,dout : std_logiv-vector(7 downto 0) ;
.
..
\\-----mux for selecting the device for use ------\\
Process(clk1,clk2,clk3)
Begin
case user_input is
when "01" =>
clk <= clk1;
din <= din1;
dout1 <= dout;
when "10" =>
clk <= clk1;
din <= din1;
dout1 <= dout;
when "11" =>
clk <= clk1;
din <= din1;
dout1 <= dout;
when others =>
clk <= '0';
din <= (others => '0');
dout <= (others => '0');
end case;
end process
--------------------------------
Process(clk)
begin
if rising-edge(clk) then
.
.
.
.\\ --- reading and writing data from\to device----\\
end process;