how to switch multiple clocks inputs for the process?

[xtcx]

hello friends!, In my application I have to select any 1 of 3 devices at the startup using user input. These 3 devices pin-outs will be connected to FPGA. I have to select only one of user choice. The pins are "clk, din, dout" pins for interface.3 devices are same....Now I have written a code to interface with this device. But my choice is to work with one depending upon user selection. I cannot use same clk for all devices. "clk" is in sensitivity list of the code. So should I hav to write 3 separate codes for 1 working device?.....I'm in need to reduce area and increase speed. So I tried to use a MUX concept to switch the clk,din,dout pins of the three to one, but Xilinx reports fatal:error only if I pass the clks of the three device into 1.....Basically i don't understand wheter clks can be switched or not?...I use "Rising_edge" of the device clk for operation.....Hence I cannot switch the desired clock for this purpose...Please help!.I have given a sample code.I pass the clock and other data pins to signal and then use that signal for device coding.I think the muxing of clock is the problem since it is again used in sensitivity list in next process.....If you could understand any please help.Thanks

Eg.,a

entity is
port(
clk1 : in std_logic;
din1 : in std_logic_vector;
dout1 : out std_logic_vector;

clk2 : in std_logic;
din2 : in std_logic_vector;
dout2 : out std_logic_vector;

clk3 : in std_logic;
din3 : in std_logic_vector;
dout3 : out std_logic_vector;
user_inpt : in std_logic_vector(1 downto 0)
);

.
.architecture .......
signal clk : std_logic;
signal din,dout : std_logiv-vector(7 downto 0) ;
.
..
\\-----mux for selecting the device for use ------\\
Process(clk1,clk2,clk3)
Begin

case user_input is
when "01" =>
clk <= clk1;
din <= din1;
dout1 <= dout;
when "10" =>
clk <= clk1;
din <= din1;
dout1 <= dout;
when "11" =>
clk <= clk1;
din <= din1;
dout1 <= dout;
when others =>
clk <= '0';
din <= (others => '0');
dout <= (others => '0');
end case;
end process
--------------------------------
Process(clk)
begin

if rising-edge(clk) then
.
.
.
.\\ --- reading and writing data from\to device----\\
end process;

 

[FvM]

Ability of multiplexing a clock is mainly a matter of the used hardware rather than a VHDL problem. With some FPGA families,
special library elements may exist for clock multiplexing. The device manuals and design compiler doc should tell.

 

[kvingle]

If you are dealing with xillinx FPGA's you can use bufgmux resource available in fpga...
It can be used as 2:1 mux for clock signals. IT can provide glitch free transition from one clk to other.
refer to bufgmux in lib.

 

[naizath12]

I guess you can try the following logic:

Reg [2:0]u1,u2,u3;
Always @(posedge clk)
Begin
case(user input):
'00' : u1 = 1; u2,u3=0;
'01' : u2 = 0; u1,u3=0;
'10' : u3 = 0; u1,u2=0;
End case
End(always loop)

Always @(posedge clk)
Begin
r1= (define a vector with clk,datain,dataout as the elements) AND u1
Similarly r2,r3;
End

I hope this Example would make things clear:
If user input =1;
Then u1=[111] u2=[000] and u3=[000]
Therefore r1=[clk,datain,dataout ]
R2,r3 = [000]

 

[xtcx]

thanks "Kvingle" and "fvm" for the idea of using BUFGMUX...I will look onto it!.....And "naizath12" I will try your logic and see if that works for clock muxing!....Thanks

 

[shitansh]

hi,

For Din and Dout pin interface you can used simple muxing, depending on user input selection, you can achive this any of mux coding style (Mux using case, conditional assignment or if...else statement).

For Clock muxing you have to little bit take care about while user gives input to select one of device there should not any glitch on clock signal, i.e. For clock muxing you must have to use Glitch Free clock switching, it is nothing but mux only with additional circuitry for glitch free switching.
One more thing if you are using special library element for Clock switching, then please take a close look toward datasheet of that element and then use it (This is only a suggetion).

For Glitch free Clock switching you can visit this topic.


If I will get time i will provide you code, but I think from this explaination you can do your self also.

HTH
--
Shitansh Vaghela

 

[xtcx]

Hi friendz!, From some of the notes which i found in the internet, it appears that the BUFGMUX is for use with two known good and working clock signals...My condition is to switch two unknown conditioned clocks which come from two wireless radio units...Completely async and you cannot predict when the device might be on...But the user is provided with the option of selecting the radio Only one time when on POWER UP....So once switched to the desired clock,it won't change....Because this mux runs for one time at power-up.So while switching the clocks,the clock maybe running or not, that depends on RADIO units....The user needs to reset if ned to select the radio again....So I guess the BUFGMUX concept wouldn't help in this case...Correct me if I'm wrong!..

Added after 6 minutes:

Thanks "Shitansh Vaghela"....I too have designed Din,Dout using 3:1 mux simply and it works good...For now, the clock is the problem...I'm not getting synthesized in my xilinx ISE tool...Well!, it shows fatal error upon when switching clocks using a mux...Now the cause of this problem seems to be unknown...Any idea about the tool error info?...there is no known answers record for this case...Thanks

 

[shitansh]

Ok,

Try to use attched clk_switch_4_1.v file for clock switching, you just have to instanciate clk_switch_4_1.v file in your VHDL module(architechture body) using component.

To make instance of VHDL file in Verilog you can refere **broken link removed**, you have to do exactly reverse way to work around.

You will able to synthesis without any problem.

If still you not able to synthesis then just pass output clock of clk_switch_4_1.v from clock buffer and then I think synthesis will pass.

HTH
--
Shitansh

 

[xtcx]

Thank you "shitansh" for your intentional help!...I will modify my code and let you update the status soon in this post!....Will use your verilog file

 

[laodao01]

Your clk's frequency ?
if less than 10M,you can use vhdl code to choose directly.