Often you will start at the top - what are the top level interfaces - so those signals will already be defined. Then, you look at what kind of precision you need in your datapath through the design, and what kind of flow control is needed. For example, if you are using video, you will need to keep track of your position, so you probably want Hvalid and vvalid signals in parrallel to the data (probably along with dvalid or y/c select for for some types of video).
But it will really differ from system to system. If you are trying to get an algorithm from matlab into an FPGA, it can be a good idea to architect the design in matlab, because then you can black box the VHDL entities and matlab functions and compare the data out from both, and ensure that the data is identical.