how to start with designing a system

[makanaky]

Hi,

I am trying to choose a system to design using VHDL for a project . I need to know what are the steps to do before writing VHDL code . What inputs should I have ( is just a description for what the system does sufficient , as that all i find when i search for projects ) . How much do designers typically take to understand the system before writing the code ?

Thanks

 

[mrflibble]

Actually I'd be interested in that as well. I've never really had any formal training with regard to HDL and the design process, so for me it's a rather organic process. It would be nice to hear from the pro's how they do things. Mostly the specification + documentation aspect would be very interesting. Lots of room for improvement there...

 

[TrickyDicky]

Often you will start at the top - what are the top level interfaces - so those signals will already be defined. Then, you look at what kind of precision you need in your datapath through the design, and what kind of flow control is needed. For example, if you are using video, you will need to keep track of your position, so you probably want Hvalid and vvalid signals in parrallel to the data (probably along with dvalid or y/c select for for some types of video).

But it will really differ from system to system. If you are trying to get an algorithm from matlab into an FPGA, it can be a good idea to architect the design in matlab, because then you can black box the VHDL entities and matlab functions and compare the data out from both, and ensure that the data is identical.

 

[mrflibble]

Do you have any links to examples of design documents? In the past I've been looking for that but came up empty. For software architecture there's plenty, but HDL not so much.

 

[TrickyDicky]

I dont have any - its been a process we've been trying to adpopt here at work.
But the theory holds out for testing - have a look at "Writing Testbenches - Functional Verification of HDL models" by Janick Bergeron.

I know its not a system design book - but is about different types of testing. This would lead on to having a well architected design.

 

[mrflibble]

Thanks for the book suggestion. While looking for it, I also noticed the author has a more recent book on SystemVerilog.

Writing Testbenches

Using SystemVerilog

I have recently completed a new version of my book on how to write testbenches using SystemVerilog. It describes the techniques that I have developed during my career as a Design Verification Engineer. Click on the book cover on the left for more details.

That one might be the ticket since I have been dabbling at using SV for verification. Well, and synthesis as well, but in my case that is mainly just interfaces and lazy port lists.

And I get the point about it being about testing but how that helps design. Design for testability and all that... So hopefully that newer SV book helps in that regard.