How to start the SOC verification of some complex sub-systems?

[smahi]

Hi All,

I have good experience on Module level verification. I am newbie to SOC verification, how we can we do complete soc verification with Processor? Is it possible to port down the unit level testcases to SOC level? if yes, how can we decide which testcases we need to port? I also have one more question in coverage, we have module level code coverage as 100%, then why we need to do coverage at soc level?

Any suggestions/ideas are welcome !

 

[artmalik]

If I understand your problem ...Module level is something of verilog code which you are verifying while by SOC level you mean the verilog is synthesized to gate level netlist which needs to verified. if you have 100% coverage on the module level you can ideally get 100% coverage on the gate level netlist. Though there is an issue if the synthesis tool has converted your module into proper gates. Synthesis tools differ in their final result depending on the coding style of verilog. So your testbenches in verilog should give 100% result.
This requires work due to quirks of synthesis tools. There are groups in companies for doing this kind of work.

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If I understand your problem ...Module level is something of verilog code which you are verifying while by SOC level you mean the verilog is synthesized to gate level netlist which needs to verified. if you have 100% coverage on the module level you can ideally get 100% coverage on the gate level netlist. Though there is an issue if the synthesis tool has converted your module into proper gates. Synthesis tools differ in their final result depending on the coding style of verilog. So your testbenches in verilog should give 100% result.
This requires work due to quirks of synthesis tools. There are groups in companies for doing this kind of work.