How to start learning system Verilog?

[vsrpkumar]

Hi

Hi
friends
i want how to start learning systemverilog.I know PSL langauage perfectly.I want to learn in ncverilog tool.can anyone give sample code for that with examples.Thanking you
kumar

 

[aji_vlsi]

Want to learn SystemVerilog (Re: Hi)

Hi
friends
i want how to start learning systemverilog.I know PSL langauage perfectly.I want to learn in ncverilog tool.can anyone give sample code for that with examples.Thanking you
kumar

Kumar,
A humble suggestion - use descriptive subject to your postings, a "Hi" is so common

For SV - there are tons of examples available off websites/books/vendor documentations. Some are:

www.abv-sva.org (SystemVerilog Assertions, similar to PSL)
www.systemverilog.us (SystemVerilog TB + Framework for efficient tesbench designs)
www.sutherland-hdl.com (SystemVerilog for Design)

Also visit: www.verificationguild.com for more on SV Testbench related discussions.

HTH
Ajeetha, CVC
www.noveldv.com

* New Book: A Pragmatic Approach to VMM Adoption www.systemverilog.us
* SystemVerilog Assertions Handbook,
* Using PSL/SUGAR
Design Verification Consultant,
Contemporary Verification Consultants Private Limited,
Bangalore, India