module testcrap ( TCLOCK,TRESET,hapi, bdayo);
//-------------------
// Module I/O Signals
//-------------------
input TCLOCK, TRESET;
input [31:0] hapi;
output [15:0]bdayo;
wire [31:0] NETX;
wire [6:0] IN;
wire [15:0] pass;
//CONTROL BLOCK1
block1 block1 (
.CLK (TCLOCK),
.RST (TRESET),
.datab (NETX[8:0]), // this goes to ctrl block
.tr1 (IN[5:0]), // goes to block2
.tr2 (IN[6]) // goes to block2
);
//CONTROL BLOCK2
block2 block2 (
.CLK (TCLOCK),
.RST (TRESET),
.datab (NETX[31:9]), // connects to ctrl block
.in2 (IN), //connects to block1 IN[6:0]
.pass_o (pass) // connect to ctrl block
);
controlblock control (
.CLK (TCLOCK),
.RST (TRESET),
.hapi (hapi), //input
.out (bdayo), //output
.pasi (pass), // recives from blk2
.netx (NETX) //recieves from blk 1 &2
);
Please notice NETX comes from block1 and 2 and goes to one bus in control block.
Also block1 has tr1 and tr2 that goes to block2... also a bus joining bus... :(
Whats wrong or missing in my code?
Please help.. thanks in advance.