How to specify the input signal in verilog?

[iVenky]

Hello I am new to modelsim and Verilog.
Here's the code for a simple d f/f


LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff IS
PORT ( d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END dff;
ARCHITECTURE behavior OF dff IS
BEGIN
PROCESS (rst, clk)
BEGIN
IF( rst='1') THEN
q<='0';
ELSIF (clk 'EVENT AND clk='1') THEN
q<=d;
END IF;
END PROCESS;
END behavior;



I want to specify the input for each of the input and find the corresponding output. I opened the Wave window in Modelsim but as I didn't give any input nothing was displayed in the output. How to give the input values??

Thanks in advance.

 

[TrickyDicky]

This is not Verilog, it is VHDL.

You need to write a testbench that instantiates this code and then drive the inputs from the testbench,

 

[iVenky]

This is not Verilog, it is VHDL.

You need to write a testbench that instantiates this code and then drive the inputs from the testbench,

Oops I thought there is no difference between verilog and VHDL. Anyway thanks.

How to drive the inputs from the testbench?
What are the steps involved in modelsim?


Thanks........