how to solve undefined signal

[nesta]

Hi VhdlExperts,

I am in the process of learning vhdl.
I am having problem with undefined signal during simulation, plz help. Below is the code and problem mentioned.


-------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity hd2_slc is
port(
b : IN std_logic_vector(5 downto 0);
c_out0 : OUT std_logic_vector(2 downto 0)
);

end hd2_slc;

architecture hh of hd2_slc is

COMPONENT node
port(
I : IN std_logic_vector(2 downto 0);
Ou : OUT std_logic_vector(2 downto 0)
);
end component;

signal c_0 :std_logic_vector(2 downto 0) ;

begin

UU_0: node port map (
I(0) => b(5),
I(1) => b(4),
I(2) => b(2),
Ou => c_0 -- This give me undefined signal (U)
-- Ou => c_out0 This one works.
);


end hh;
----------------------------------------------


Why does the above code show Undefined signal (U) in the simulation for c_out vector. i know that if i port map Ou => c_out0 it works well.
But my requirement is to use a local signal and after some processing assign it to c_out0 vector.

Kindly suggest what am i doing wrong, how to use a different signal to port map with the Ou vector.

Thanks,
Nesta

 

[imbichie]

Hi,

Have you try the simulation by giving initial value of 'c_0' as ''000", Means
signal c_0 : std_logic_vector(2 downto 0) := "000";
This may replace the Unknown Problem.

Otherwise go with adding a reset pin

 

[TrickyDicky]

It does not mean undefined - it is uninitialized. It means it has not been assigned a value yet.

 

[rca]

the question is what is the relation between input pins I and output pin Ou, and also at which values the pin b is driven in your test bench.