How to solve this FF/Latch trimming warning (XST 1895)?

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mindstream

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I get the following warning during synthesis each time. is it serious?

If it is serious can someone tell me how to correct this problem.

o2_2 is a 26bit signal
i did the coding in verilog Its basically for a set of 8 complex multipliers and o2_2 is one of the outputs . none of the other output signals are showing this warning.

If needed i can attach the verilog code as well.
 

FF/Latch Trimming

In my opinion it is quite possible you did some mistake in your design so the FF/latches shown do not change their states at all.
I have to say that although I work with Xilinx and VHDL I do not know Verilog.
 

Re: FF/Latch Trimming

It sounds like you created latches with a defined value of zero.

Attach your code so we can see what you did.

E
 

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