How to solve this error in Questasim simulation: Fatal: (vsim-3695)

[tingtaox]

Hello

I encountered this error when I was writing a random-constrained verification testbench. It occurred at the connection between DUT and testbench, more precisely the program block.

The error is : Fatal: (vsim-3695): The interface port 'in_intf' must be passed an actual interface, when I ran the code on Questa Sim 10.2.

My code is very simple, shown as below:

module top;
intf in_intf();
switch(in_intf);
test(in_intf);
endmodule

module switch(intf in_intf);
assign in_intf.mp.b = in_intf.mp.a;
endmodule

interface intf();
logic a, b;
modport mp(output a, input b);
endinterface

program test(intf.mp in_intf);
virtual intf.mp intf0 = in_intf; 
...
endprogram

I actually read some posts saying the causes may be incomplete port connection or type mismatch. But I think the connection is complete and their types match. Is there other way to solve it?

Thanks in advance.

 

[dave_59]

I did not get the error message you show, but there are a number of other syntax errors with your code.

There are no required instance names in the instantiation of switch and test. It should be:

module top;
  intf in_intf();
  switch [B]U1[/B](in_intf);
  test [B]U2[/B](in_intf);
endmodule

Modport names should not be referenced in hierarchical paths. They should only be used in port declarations, port connections, and virtual interface declarations.

module switch(intf[B].mp[/B] in_intf);
  assign in_intf.b = in_intf.a;
endmodule

Finally, I recommend against ever using program blocks in SystemVerilog.