how to solve the problem: if setup time is not enough?

[bigrice911]

HI, it's an IC interview question, can anyone give me a perfect answer?

When your design's setup time is not enough, what will you do?
How to design a 5.5 frequency divder with some simple CMOS transistors?

 

[dexter_ex_2ks]

Hi,
In my opinion I think u can't design a 5.5 frequency divider with "some simple CMOS transistors". My proposal to u is to use a PLL, wich is a pretty complex circuit, but I think u can manage (if not ask on this forum, and u'll get answers).

 

[bigrice911]

I said I need to use PLL which made the interviewer very unhappy... Maybe there's a way which I don't know.

 

[Nir Dahan]

Whenever you encounter a problem like "design a divide by ..." this is how you solve it.
1) draw original clock
2) draw target desired clock
3) watch if the new desired clock can be derived from the original clock - this means if the ALL rising edges and the falling edges of the new clock ALIGN with the original clock.

look at the diagram below I made.
the original clock is on top.
the interviewer asked a divide by 5.5.
this means that there should be 4 clock cycles within 22 original clock cycles 5.5*4=22

First lets look at the signal second from the top. If you wanna be a bit nasty you can offer him that solution - it is the easiest. you just pick 4 edges of the original clock for each 22 original clock cycles.
That is A solution but it is not one I would use. But as an interviewer I guess I would be happy to see someone interpreting the question like this.
to sum up - second signal from top selects 4 edges withing 22 original clock cycles.

next - 3rd signal from top. Here we want those 4 clock edges EVENLY distributed in time. again this is done by SELECTION of original clock edges. draw the DESIRED clock pattern and you will realize which edges to choose from. Notice that sometimes you gotta choose negative edges to trigger a positive edge in the desired clock - this can become tricky!
to sum up - 3rd signal from top divides the desired clock edges in time (orange arrows show the cycle time) notice how the duty cycle is NOT 50-50

4th signal from top - what if the interviewer wants a 50% duty cycle divide by 5.5 circuit?
what do we do - yes, we draw the DESIRED clock pattern. We notice something strange, some edges of the desired clock do not correspond to ANY original edges (red vertical lines in diagram)!! this means that with only simple memory elements this can't be done.

This is actually a very neat question IMHO. it can show the thinking process and a proof of impossibility is always nice.

for more info check my posts here
https://asicdigitaldesign.wordpress...w-question-for-logic-design-a-mini-challenge/
https://asicdigitaldesign.wordpress...cal-interview-question-the-standard-solution/
https://asicdigitaldesign.wordpress.com/2008/01/31/ultimate-technical-interview-question-take-2/

hope this helps!

ND.
https://asicdigitaldesign.wordpress.com/