I am reviewing a 4MHz PLL with 6 stages ring of Gm-C cells.
The problems is gm value of these cells varies with process;
and even worse when temperature changes.
Cant we use a constant-gm bias to bias the gm cells? I have seen it maintain constant-gm when I used it in a LNA. Just wondering... Let me know if this is wrong.
In the case of PLL, GM bias circuit are mainly controlled by output voltage
of loop filter which we called "Vtune".
With differnent Vtune, the GM bias should control the GM cell bias current
so as to reduce PFD (phase frequency detector) error.
I have no idea how to compensate (vs temperature or process) practically.
So I posted the question.
Thanks a lot for your suggestion.