How to simulate 'X' in conditional statements

[weetabixharry]

When debugging VHDL designs, I often like to set my data signals to 'X' (i.e. "Unknown") whenever the driving signal is invalid. For example:

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Code VHDL - [expand]
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process (clk) is
begin
    if rising_edge(clk) then
        if in_valid = '1' then
            out_data <= in_data;
        else
            out_data <= (others => 'X');
        end if;
    end if;
end process;

---

By doing this, it means that if an invalid data value is ever used, then a load of 'X' values will propagate thereafter (clearly visible as red lines in my Modelsim testbench simulation).

However, this does not work if I want to multiplex two data signals, based on a condition (e.g. greater than, less than, equal) that may contain 'X' values. For example, if condition_a or condition_b is assigned (others => 'X') in the following:

---

Code VHDL - [expand]
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process (clk) is
begin
    if rising_edge(clk) then
        if condition_a = condition_b then
            out_data <= in_data_x;
        else
            out_data <= in_data_y;
        end if;
    end if;
end process;

---

then out_data will not be assigned as "Unknown". Instead, Modelsim issues a warning, assumes the condition to be false and so the result is: out_data <= in_data_x... while what I wanted was out_data <= (others => 'X').

As a horrible hack, the following will do what I want:

---

Code VHDL - [expand]
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process (clk) is
    variable x_check : std_logic;
begin
    if rising_edge(clk) then
        x_check := condition_a(0) or not condition_a(0)
                    or condition_b(0) or not condition_b(0);
        if condition_a = condition_b then
            out_data <= in_data_x and (in_data_x'length-1 downto 0 => x_check);
        else
            out_data <= in_data_y and (in_data_x'length-1 downto 0 => x_check);
        end if;
    end if;
end process;

---

This works because any expression like "a or not a" will always return '1' unless the signals are unknown. Therefore if I "and" the result with my data, then an "Unknown" condition will yield an "Unknown" out_data.

However, this is a really ugly hack and I assume there must be a better way. If anyone here knows a better way (or can think of one) I would really love to know!

 

[Dinesh Varma4]

Well try this method ..
include condition_a and condition_b in process sensitive list

And by the way its really not a good idea to have 'X' as an output, works for the simulation but not when you are dumping the code on hardware

 

[weetabixharry]

include condition_a and condition_b in process sensitive list

Could you explain why this helps?

And by the way its really not a good idea to have 'X' as an output, works for the simulation but not when you are dumping the code on hardware

It is fine for debugging.

 

[Dinesh Varma4]

anything that your process needs to know about changes of inputs or signals should be in the sensitivity list

 

[jt_eaton]

You are trying to write a piece of code that does two different things and are doing a lousy job at both of them. You are trying to build a protocol checker on top of the code that is also synthesized into gates. You need to split these into two seperate pieces. Create one piece soley for synthesys. If in_valid is not active then repeat the old value of out_data. Then write a completely seperate protocol checker that detects the error conditions and fires an error into the log file. This code is only used for simulations.

Never try to use x's to catch errors. They work "most" of the time but in todays world that is not good enough anymore

 

[weetabixharry]

write a completely separate protocol checker that detects the error conditions and fires an error into the log file. This code is only used for simulations.

Yes, this is exactly what I want to do. Could you offer any pointers as to how this can be done? I have a fair bit of VHDL experience, but don't know of any better way of doing this.

Many thanks.