Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to simulate the DNL and INL of a ADC?

Status
Not open for further replies.

benchen

Member level 2
Joined
Sep 9, 2005
Messages
42
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,286
Activity points
1,605
An ADC based on binary weighted capacitor array needs to simulate its DNL and INL. I think the most important factor affecting the DNL and INL is the mismatch of the capacitor. Should I employ Mento carlo analysis ? And how to caculate the DNL and INL after every times of running?
 

wdd

Member level 3
Joined
Nov 12, 2004
Messages
66
Helped
8
Reputation
16
Reaction score
1
Trophy points
1,288
Activity points
510
benchen said:
An ADC based on binary weighted capacitor array needs to simulate its DNL and INL. I think the most important factor affecting the DNL and INL is the mismatch of the capacitor. Should I employ Mento carlo analysis ? And how to caculate the DNL and INL after every times of running?

maybe what you say is a current-steering DAC, for DNL and INL you can input a sinewave or a ramp, then process the data by a program based on code density testing or the transition level directly. But it'c time hungry.
Monte Carlo maybe work, more commonly, a matlab program is used with a standard deviation σ relevant to process and circuit to verify the performance.

Best
 

kidman561

Newbie level 5
Joined
Sep 7, 2004
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
63
you can use the hspice matlab tools.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top