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How to simulate the DNL and INL of a ADC?

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benchen

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An ADC based on binary weighted capacitor array needs to simulate its DNL and INL. I think the most important factor affecting the DNL and INL is the mismatch of the capacitor. Should I employ Mento carlo analysis ? And how to caculate the DNL and INL after every times of running?
 

wdd

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benchen said:
An ADC based on binary weighted capacitor array needs to simulate its DNL and INL. I think the most important factor affecting the DNL and INL is the mismatch of the capacitor. Should I employ Mento carlo analysis ? And how to caculate the DNL and INL after every times of running?

maybe what you say is a current-steering DAC, for DNL and INL you can input a sinewave or a ramp, then process the data by a program based on code density testing or the transition level directly. But it'c time hungry.
Monte Carlo maybe work, more commonly, a matlab program is used with a standard deviation σ relevant to process and circuit to verify the performance.

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kidman561

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you can use the hspice matlab tools.
 

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