How to simulate SPI interface in ADE?

[walker5678]

vpwl format

I am simulating a circuit with SPI interface in analog design environment.
There need DIN and DCLK singal input. I am using vpwl and vpulse to generate these signal, however if I want to simulate different clock frequency, i must remodify every parameters of the vpwl and vpulse source, which is very boring.
Anybody knows how to simulate such digital interface in ADE , or , is there any other better tools to simulate it?
Thanks a lot.

 

[erikl]

vpwl variable

... if I want to simulate different clock frequency, i must remodify every parameters of the vpwl and vpulse source, which is very boring.

Shouldn't it be possible to relate all parameters to a single parameter (clock frequency), then sweep this one?

 

[walker5678]

vpwl support design variable

yes, i am also thinking that, but how to write the PWL file? What is the format of PWL file?
If I set a variable called frequency in the PWL file, i can use vpwlf source to generate the singal.

 

[JoannesPaulus]

vpwlf variable

use the vpulse instead of the vpwlf and put your parameters in the delay, rise time, fall time pulse width and period boxes. For instance you can define:
dclk_freq=1e6, dclk_tp=1/dclk_freq, dclk_tr=1e-9, dclk_tf=1e-9, and dclk_tw=0.5*dclk_tp-dclk_tr.
Then you only need to change dclk_freq and your new clock is ready!

 

[walker5678]

ade vpwlf format

However, for DCLK, between every 8 clocks there is a blanking time, which is also need to be adjust.

and DIN is not a pulse , but a constant logical level during one whole clock cycle.

Added after 1 hours 13 minutes:

anybody has an example pwl file , please kindly share. Thanks !

 

[erikl]

spi interface design

What is the format of PWL file?

anybody has an example pwl file , please kindly share. Thanks !

The format is: <time> <white space> <voltage>
i.e.:
<time0> <voltage0>
<time1> <voltage1>
............. ................

... however - at least in my setUp - variables in the vpwlf file are not supported. I used OS tools (Unix, Linux) to calculate the real values from the parameters.
Good luck! erikl

 

[pit1000]

spi profile clock

If you use MMSIM 6.0 or higher version it is possible to set digital signals by means of digital vector file otherwise better to use ULTRASIM.

 

[JoannesPaulus]

vpwl parameters

For the blanking time, you could use a second signal source and do a logical AND with DCLK.

 

[walker5678]

hi, erikl:
thanks, it works.

 

[erikl]

hi, erikl:
thanks, it works.
BTW, you can use evalstring(desVar(\"vdd\")) to let pwl file support design variable. vdd is an example, it could be any variable name.

And thank you for your feedback, walker!