How to simulate PLL's locking time?

[icsoul]

How to simulate PLL's locking time?

How to simulate PLL's jitter?

Detailed demenstration will be very good

Any papers or related data are also welcome.

Thank you!~

 

[safwatonline]

to simulate lock time , i guess u should monitor the Vctrl after changing the divider from Nmin to Nmax and see Vctrl settle to a certain error.

 

[khouly]

yeah use the transient simulation , and change the divider and monitor control voltage , by this u can get the lock time , this is the most accurate

khouly

 

[icsoul]

to simulate lock time , i guess u should monitor the Vctrl after changing the divider from Nmin to Nmax and see Vctrl settle to a certain error.

It is a method.

But the control voltage in lock state is different for reference input of different frequency. Then what reference value of control voltage should be set for different freq?

Added after 5 minutes:

yeah use the transient simulation , and change the divider and monitor control voltage , by this u can get the lock time , this is the most accurate

khouly

I think the lock time must be measured in the control voltage curve under this method. That means it is not so accurate

 

[LvW]

Mostly, I simulate on block level with VISSIM.

The pdf-attachement shows the VCO-Control voltage vs. time.
In this example, lock-in time is 2 msec.

Here is an alternative method:
Create a Lissajous-picture with the input and the VCO frequnecy.
If both are equal in frequency but out of phase by 90 deg. there will be a circle on the display when the loop has locked.

Perhaps this helps.
LvW

 

[safwatonline]

i think u should run the VCO in open loop and get the freq vs Vctrl and use this curve as ur reference.

 

[rillyxue]

run trans in spectre or .tran in hspice, and see vcontrol voltage or see the two input signal of pd/pfd.

 

[icsoul]

Mostly, I simulate on block level with VISSIM.

The pdf-attachement shows the VCO-Control voltage vs. time.
In this example, lock-in time is 2 msec.

Here is an alternative method:
Create a Lissajous-picture with the input and the VCO frequnecy.
If both are equal in frequency but out of phase by 90 deg. there will be a circle on the display when the loop has locked.

Perhaps this helps.
LvW

Hi, LvW

Is the simulation in the attachment a behavior level or transistor level?

What's the meanings of "Lissajous-picture"?

 

[LvW]

Its on behaviour level based on a block diagram with linear units.

Lissajous: Suppose you have two identical frequencies which are out of phase by 90 deg . Display one signal NOT vs. time but vs. the other signal on the x-axis.
In this case you will get a picture like a circle if both amplitudes are equal; otherwise it will be some sort of ellipse.
You can do this with each scope and by simulation as well ("choose x-axis")