[SOLVED] how to simulate physically synthesized verilog code in modelsim

[hamidmoallemi]

Hi
I have written a verilog code and simulated it functionally in Modelsim,
I have used Cadence PKS-shell to synthesize the verilog code in TSMC 0.18 um,
now i want to simulate the synthesized code with real cell delays,
can i do it in Modelsim ?
I think I will need some technology libraries but i dont know which files in which format!


Can any one help me on this?

Regards
Hamid Moallemi

 

[vash77]

u can synrthesize your code using projrct navigator tool.ur simulated model u can use it .