how to simulate netlists such as EDIF and NGC files ?

[omidsht]

Hi ,
If we want to instantiate an EDIF or NGC netlist file in a vhdl code , then how can we simulate it in modelsim or activehdl ?
in modelsim when i copy the EDIF file or NGC file in my folder , after i write a vhdl code and instantiate it as a component , when starting to simulate , it says : it is not bound ! seems that it does not see or recognize the netlist !
so what to do ?
thanks in advanced.

 

[farhada]

HI,
I don't think you can simulate your design that easily, you maybe able to add those EDIF files and NGC file into your final design and when the design is fully routed and mapped, you can create a post-layout simulation of your design and that way you can simulate the whole design.

One simple way is to create small project for each EDIF and NGC file and simulate it that way.

Hope you find this answer helpful,

Cheers,
/Farhad Abdolian

 

[omidsht]

Hi Dear Farhad , I synthezied my vhdl code with ISE9.2 and I created a
post-synthesis simulation model (or PAR). then when i want to simualte that
post-synthesis model (or PAR) , after some time ellapsed in simulation (very short
, about 20000 ns) it gets the following error and simulation stops:
errorvsim-3601)iteration limit reached at time 20200 ns.
note:delays were truncated during elaboration of the design.
what shall i do? thanks in advanced.
(are u iranian? i am).

 

[farhada]

Hi Omid,
Yes, I am Iranian, but been living abroad for the past 25 years.

I found this about your error message:

This error usually indicates that ModelSim is stuck in an infinite loop. In VHDL, this can happen when a signal is placed in the sensitivity list and this signal is changed in the process. The signal changes, triggering the process, which changes the signal, which again triggers the process and the cycle continues.

The following is a simple example of a process that causes an infinite loop:

PROCESS (count)
BEGIN
count <= not count;
END PROCESS;

Take a look at your code and see if you can find any such issue, and try to locate it into your design. One way is to find the exact location of this error, then find the signal that is causing it, then use the FPGA editor to search for this signal and locate it in the block, if you are lucky, it will be in one of your own blocks, or else, you have to find another solution such as adding extra delays for the signals etc.

Hope this helps,

bA ehterAm,
/Farhhad Abdolian

Added after 2 minutes:

Also look at the following discussion, it seems that you can bypass this problem by using a SDF file!



Added after 2 minutes:

ALso look at this:

This issue is due to a ring oscillator in the DCM Standby Logic not toggling when used with UniSim simulation model. When using an SPI-4.2 Core with the DCM Standby Logic, the only way to simulate the core is to perform timing simulation which uses the SimPrim model, and you must simulate with the SDF file.

If you are not quite ready to perform timing simulation and would like to perform functional simulation, please use the SPI-4.2 Core without the DCM Standby Logic and replace it with the SPI-4.2 Core netlist with the DCM Standby Logic when you are ready to perform timing simulation. There are no functional differences between the two NGC netlists other than the DCM Standby Logic, and you should be able to simply replace the NGC netlist without making any design changes. Once the netlist is replaced, you will need to re-run the implementation from NGDBUILD command.

For more information on simulating the SPI-4.2, see the "Simulating and Implementing the Core" section of the SPI-4.2 User Guide:
https://www.xilinx.com/support/mysupport.htm